Circuits used for memory applications generally require a small cell size in order to optimize the density of the memory array. As the size of a memory cell is reduced, a trade-off is made between the cell current, which determines sensing speed, and the cell size. A higher cell current results in a faster sensing speed, but also increases cell size and hence the size of the memory array. Conversely, a small cell size reduces the size of the array, but also reduces the cell current and therefore, the sensing speed.
In erasable programmable logic devices, such as EPALs and EEPALs, sensing speed and programmability (for adequate sense margin) have a much greater importance than cell size, since the EPROM or EEPROM array contributes a relatively small portion of the size of the total device. Previously, 2-transistor cells have been developed for EPROM and EPAL devices using NSAG (N-channel self-aligned gate) technology wherein the source and drain of the sources and drains of the memory cell array are self-aligned with the gates.
The 2-transistor cell provides significant advantages over 1-transistor cell. The 2-transistor cell has a common floating gate which spans each transistor. The width of the floating gate of the first transistor (the read transistor) may be optimized for a high IDS for increased sensing speed. Typically, this is accomplished by using a wide gate over the read transistor. Further, the second transistor (the "program" or "write" transistor) can be optimized for optimum programmability. Typically, this is accomplished by using a narrow gate for low programming current requirements.
Nonetheless, the NSAG 2-transistor cell has several shortcomings. In the NSAG 2-transistor cell, contacts are needed for each pair of drains (drains of adjacent cells may share a contact) and for every several sources in the array. The need for contacts increases the size of the cell, and the size of the larger source/drain regions. Using 1-micron technology, the cell area of the NSAG 2-transistor cell is approximately 96 microns.sup.2.
Therefore, a need has arisen in the industry for a 2-transistor non-volatile memory cell with reduced size, without sacrificing sensing speed or programmability.